Z80 Instruction Set — Hardware


DI
EI
HALT
IM
IN
IND
INDR
INI
INIR
OTDR
OTIR
OUT
OUTD
OUTI

DI

DI
Operation Resets both interrupt flip-flops, thus preventing maskable interrupts from triggering.
Op Code 11110011
T States 4

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EI

EI
Operation Sets both interrupt flip-flops, thus allowing maskable interrupts to occur. An interrupt will not occur until after the immediatedly following instruction.
Op Code 11111011
T States 4

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HALT

HALT
Operation Suspends CPU operation until an interrupt or reset occurs.
Op Code 01110110
T States 4

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IM

IM 0
Operation Sets interrupt mode 0.
Op Code 11101101 : 01000110
T States 8

IM 1
Operation Sets interrupt mode 1.
Op Code 11101101 : 01010110
T States 8

IM 2
Operation Sets interrupt mode 2.
Op Code 11101101 : 01011110
T States 4

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IN

IN A,(imm8)
Operation A byte from port imm8 is written to A.
Op Code 11011011 : [imm8]
T States 11

IN reg8,(C)
Operation A byte from port C is written to reg8.
Op Code 11101011 : 01[reg8]000
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
Flags S Z are affected as defined
H N are reset
P/V is parity
C is not affected
T States 12

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IND

IND
Operation A byte from port C is written to the memory location pointed to by HL. HL and B are then decremented.
Op Code 11101101 : 10101010
Flags S H P/V are scrambled
Z is set if B becomes zero
N is set
C is not affected
T States 16

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INDR

INDR
Operation A byte from port C is written to the memory location pointed to by HL. HL and B are then decremented. If B is not zero, this operation is repeated.
Op Code 11101101 : 10111010
Flags S H P/V are scrambled
Z N are set
C is not affected
T States If B != 0: 21
If B == 0: 16

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INI

INI
Operation A byte from port C is written to the memory location pointed to by HL. HL is incremented and B is decremented.
Op Code 11101101 : 10100010
Flags S H P/V are scrambled
Z is set if B becomes zero
N is set
C is not affected
T States 16

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INIR

INIR
Operation A byte from port C is written to the memory location pointed to by HL. HL is incremented and B is decremented. If B is not zero, this operation is repeated.
Op Code 11101101 : 10110010
Flags S H P/V are scrambled
Z N are set
C is not affected
T States If B != 0: 21
If B == 0: 16

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OTDR

OTDR
Operation A byte from the memory location pointed to by HL is written to port C. HL and B are then decremented. If B is not zero, this operation is repeated.
Op Code 11101101 : 10111011
Flags S H P/V are scrambled
Z N are set
C is not affected
T States If B != 0: 21
If B == 0: 16

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OTIR

OTIR
Operation A byte from the memory location pointed to by HL is written to port C. HL is incremented and B is decremented. If B is not zero, this operation is repeated.
Op Code 11101101 : 10110011
Flags S H P/V are scrambled
Z N are set
C is not affected
T States If B != 0: 21
If B == 0: 16

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OUT

OUT (imm8),A
Operation The value of A is written to port imm8.
Op Code 11010011 : [imm8]
T States 11

OUT (C),reg8
Operation The value of reg8 is written to port C.
Op Code 11101011 : 01[reg8]001
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
T States 12

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OUTD

OUTD
Operation A byte from the memory location pointed to by HL is written to port C. HL and B are then decremented.
Op Code 11101101 : 10101011
Flags S H P/V are scrambled
Z is set if B becomes zero
N is set
C is not affected
T States 16

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OUTI

OUTI
Operation A byte from the memory location pointed to by HL is written to port C. HL is incremented and B is decremented.
Op Code 11101101 : 10100011
Flags S H P/V are scrambled
Z is set if B becomes zero
N is set
C is not affected
T States 16

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This is part of Learn TI-83 Plus Assembly In 28 Days
Copyright (c) 2002, 2003, 2004 Sean McLaughlin
See the file gfdl.html for copying conditions