Z80 Instruction Set — Bit

AND

AND reg₈

Operation	Bitwise AND on A with reg8.
Op Code	10100[reg8] Register Bit Field A 111 B 000 C 001 D 010 E 011 H 100 L 101 (HL) 110
Flags	S Z are affected as defined H is set P/V is parity N C are reset
T States	4 or 7 (HL)

AND imm₈

Operation	Bitwise AND on A with imm8.
Op Code	11100110 : [imm8]
Flags	S Z are affected as defined H is set P/V is parity N C are reset
T States	7

AND (reg_index + ofs₈)

Operation	Bitwise AND on A with the data at the memory location pointed to by regindex plus ofs8.
Op Code	[regindex] : 10100110 [ofs8] Register Bit Field IX 11011101 IY 11111101
Flags	S Z are affected as defined H is set P/V is parity N C are reset
T States	19

BIT

BIT imm₃,reg₈

Operation	Tests bit imm3 of reg8.
Op Code	11001011 : 01[imm3][reg8] Register Bit Field A 111 B 000 C 001 D 010 E 011 H 100 L 101 (HL) 110
Flags	S P/V are scrambled Z is affected as defined H is set N is cleared C is unaffected
T States	8 or 12 (HL)

BIT imm₃,(reg_index + ofs₈)

Operation	Tests bit imm3 of the data at the memory location pointed to by regindex plus ofs8.
Op Code	[regindex] : 11001011 : [ofs8] : 01[imm3110 Register Bit Field IX 11011101 IY 11111101
Flags	S P/V are scrambled Z is affected as defined H is set N is cleared C is unaffected
T States	23

CCF

CCF

Operation	Inverts the value of the carry flag.
Op Code	00111111
Flags	S Z P/V are unaffected H is the carry before operation N is reset See instruction for C
T States	4

OR

OR reg₈

Operation	Bitwise OR on A with reg8.
Op Code	10110[reg8] Register Bit Field A 111 B 000 C 001 D 010 E 011 H 100 L 101 (HL) 110
Flags	S Z are affected as defined P/V is parity H N C are reset
T States	4 or 7 (HL)

OR imm₈

Operation	Bitwise OR on A with imm8.
Op Code	11110110 : [imm8]
Flags	S Z are affected as defined P/V is parity H N C are reset
T States	7

OR (reg_index + ofs₈)

Operation	Bitwise OR on A with the data at the memory location pointed to by regindex plus ofs8.
Op Code	[regindex] : 10110110 [ofs8] Register Bit Field IX 11011101 IY 11111101
Flags	S Z are affected as defined P/V is parity H N C are reset
T States	19

RES

RES imm₃,reg₈

Operation	Resets bit imm3 of reg8.
Op Code	11001011 : 10[imm3][reg8] Register Bit Field A 111 B 000 C 001 D 010 E 011 H 100 L 101 (HL) 110
T States	8 or 15 (HL)

RES imm₃,(reg_index + ofs₈)

Operation	Resets bit imm3 of the value at the memory location pointed to by regindex plus ofs8.
Op Code	[regindex] : 11001011 : [ofs8] : 10[imm3]110
Flags	Not affected
T States	23

SCF

SCF

Operation	Sets the carry flag.
Op Code	00110111
Flags	S Z P/V are unaffected H N are reset C is set
T States	4

SET

SET imm₃,reg₈

Operation	Sets bit imm3 of reg8.
Op Code	11001011 : 11[imm3][reg8] Register Bit Field A 111 B 000 C 001 D 010 E 011 H 100 L 101 (HL) 110
T States	8 or 15 (HL)

SET imm₃,(reg_index + ofs₈)

Operation	Sets bit imm3 of the value at the memory location pointed to by regindex plus ofs8.
Op Code	[regindex] : 11001011 : [ofs8] : 11[imm3]110
Flags	Not affected
T States	23

XOR

XOR reg₈

Operation	Bitwise XOR on A with reg8.
Op Code	10101[reg8] Register Bit Field A 111 B 000 C 001 D 010 E 011 H 100 L 101 (HL) 110
Flags	S Z are affected as defined H is set P/V is parity N C are reset
T States	4 or 7 (HL)

XOR imm₈

Operation	Bitwise XOR on A with imm8.
Op Code	11101110 : [imm8]
Flags	S Z are affected as defined H is set P/V is parity N C are reset
T States	7

XOR (reg_index + ofs₈)

Operation	Bitwise XOR on A with the data at the memory location pointed to by regindex plus ofs8.
Op Code	[regindex] : 10101110 [ofs8] Register Bit Field IX 11011101 IY 11111101
Flags	S Z are affected as defined H is set P/V is parity N C are reset
T States	19