Z80 Instruction Set — Arithmetic


ADC
ADD
CP
CPD
CPDR
CPI
CPIR
CPL
DAA
DEC
INC
NEG
SBC
SUB

ADC

ADC A,reg8
Operation reg8 and the carry flag are added to A.
Op Code 10001[reg8]
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H C are affected as defined
P/V detects overflow
N is reset
T States 4 or 7 (HL)

ADC A,imm8
Operation The immediate value and the carry flag are added to A.
Op Code 11001110 : [imm8]
Flags S Z H C are affected as defined
P/V detects overflow
N is reset
T States 7

ADC A,(regindex + ofs8)
Operation The value pointed to by index register regindex plus ofs8, and the carry flag, are added to A.
Op Code [regindex] : 10001110 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101
Flags S Z H C are affected as defined
P/V detects overflow
N is reset
T States 19

ADC HL,reg16
Operation The value of reg16 and the carry flag are added to HL.
Op Code 11101101 : 01[reg16]1010
Register Bit Field
BC 00
DE 01
HL 10
SP 11
Flags S Z C are affected as defined
P/V detects overflow
H is set if there is a carry out of bit 11
N is reset
T States 15

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ADD

ADD A,reg8
Operation Adds reg8 to A.
Op Code 10000[reg8]
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H C are affected as defined
P/V detects overflow
N is cleared
T States 4 or 7 (HL)

ADD A,imm8
Operation The immediate value is added to A.
Op Code 11000110 : [imm8]
Flags S Z H C are affected as defined
P/V detects overflow
N is cleared
T States 7

ADD A,(regindex + ofs8)
Operation Adds the value of the memory location pointed to by regindex plus ofs8 to A.
Op Code [regindex] : 10000110 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101
Flags S Z H C are affected as defined
P/V detects overflow
N is cleared
T States 19

ADD HL,reg16
Operation The value of reg16 is added to HL.
Op Code 00[reg16]1001
Register Bit Field
BC 00
DE 01
HL 10
SP 11
Flags S Z P/V are unaffected
C is affected as defined
H is set if there is a carry out of bit 11
N is reset
T States 11

ADD IX,reg16
Operation The value of reg16 is added to IX.
Op Code 11011101 : 00[reg16]1001
Register Bit Field
BC 00
DE 01
IX 10
SP 11
Flags S Z P/V are unaffected
C is affected as defined
H is set if there is a carry out of bit 11
N is reset
T States 15

ADD IY,reg16
Operation The value of reg16 is added to IY.
Op Code 11111101 : 00[reg16]1001
Register Bit Field
BC 00
DE 01
IY 10
SP 11
Flags S Z P/V are unaffected
C is affected as defined
H is set if there is a carry out of bit 11
N is reset
T States 15

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CP

CP reg8
Operation Subtracts reg8 from A and affects flags according to the result. A is not modified.
Op Code 10111[reg8]
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 4 or 7 (HL)

CP imm8
Operation Subtracts the immediate value from A and affects flags according to the result. A is not modified.
Op Code 11111110 : [imm8]
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 7

CP (regindex + ofs8)
Operation Subtracts the memory value pointed to by regindex plus ofs8 from A and affects the flags according to the result. A is not modified.
Op Code [regindex] : 10111110 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 19

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CPD

CPD
Operation Compares the value of the memory location pointed to by HL with A. HL and BC are then decremented.
Op Code 11101101 : 10101001
Flags S Z H are affected as defined
P/V is reset if BC becomes zero
N is set
C is unaffected
T States 16

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CPDR

CPDR
Operation Compares the value of the memory location pointed to by HL with A. HL and BC are then decremented. If BC is not zero and Z is not set, this operation is repeated. Interrupts can trigger while this instruction is processing.
Op Code 11101101 : 10111001
Flags S Z H are affected as defined
P/V is reset if BC becomes zero
N is set
C is unaffected
T States If BC != 0 and Z is reset: 21
If BC == 0 or Z is set: 16

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CPI

CPI
Operation Compares the value of the memory location pointed to by HL with A. HL is incremented and BC is decremented.
Op Code 11101101 : 10100001
Flags S Z H are affected as defined
P/V is reset if BC becomes zero
N is set
C is unaffected
T States 16

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CPIR

CPIR
Operation Compares the value of the memory location pointed to by HL with A. HL is incremented and BC is decremented. If BC is not zero and Z is not set, this operation is repeated. Interrupts can trigger while this instruction is processing.
Op Code 11101101 : 10110001
Flags S Z H are affected as defined
P/V is reset if BC becomes zero
N is set
C is unaffected
T States If BC != 0 and Z is reset: 21
If BC == 0 or Z is set: 16

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CPL

CPL
Operation The contents of A are inverted (one's complement).
Op Code 00101111
Flags S Z P/V C are not affected
H N are set
T States 4

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DAA

DAA
Operation Adjusts A for BCD addition and subtraction operations.
N Flag C Flag Bit 7-4 H Flag Bit 3-0 Number
Added
Output
C Flag
0 0
0
0
0
0
0
1
1
1
9-0
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3
0
0
1
0
0
1
0
0
1
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
00
06
06
60
66
66
60
66
66
1
1
1
0
0
0
0
0
0
1 0
0
1
1
0-9
0-8
7-F
6-7
0
1
0
1
0-9
6-F
0-9
6-F
00
FA
A0
9A
0
0
1
1
Op Code 00100111
Flags S Z are affected as defined
P/V is parity
N is unaffected
See instruction for H C
T States 4

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DEC

DEC reg8
Operation Subtracts one from reg8.
Op Code 00[reg8]101
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H are affected as defined
P/V is set if operand was $80 before operation
N is set
C is unaffected
T States 4 or 11 (HL)

DEC (regindex + ofs8)
Operation Subtracts one from the memory location pointed to by regindex plus ofs8.
Op Code [regindex] : 00110101 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101
Flags S Z H are affected as defined
P/V is set is operand was $80 before operation
N is set
C is unaffected
T States 23

DEC reg16
Operation Subtracts one from reg16.
Op Code 00[reg16]1011
Register Bit Field
BC 00
DE 01
HL 10
SP 11
T States 6

DEC regindex
Operation Subtracts one from regindex.
Op Code [regindex] : 00101011
Register Bit Field
IX 11011101
IY 11111101
T States 10

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INC

INC reg8
Operation Adds one to reg8.
Op Code 00[reg8]100
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H are affected as defined
P/V is set is operand was $7F before operation
C is unaffected
T States 4 or 11 (HL)

INC (regindex + ofs8)
Operation Adds one to the memory location pointed to by regindex plus ofs8.
Op Code [regindex] : 00110100 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101
Flags S Z H are affected as defined
P/V is set is operand was $7F before operation
C is unaffected
T States 23

INC reg16
Operation Adds one to reg16.
Op Code 00[reg16]0011
Register Bit Field
BC 00
DE 01
HL 10
SP 11
T States 6

INC regindex
Operation Adds one to regindex.
Op Code [regindex] : 00100011
Register Bit Field
IX 11011101
IY 11111101
T States 10

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NEG

NEG
Operation The contents of A are negated (two's complement). Operation is the same as subtracting A from zero.
Op Code 11101101 : 01000100
Flags S Z H are affected as defined
P/V is set if A was $80 before operation
N is set
C is set if A was not $00 before operation
T States 8

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SBC

SBC A,reg8
Operation Subtracts reg8 and the carry flag from A.
Op Code 10011[reg8]
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 4 or 7 (HL)

SBC A,imm8
Operation Subtracts the immediate value and the carry flag from A.
Op Code 11011110 : [imm8]
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 7

SBC A,(regindex + ofs8)
Operation Subtracts the value at the memory location pointed to by regindex plus ofs8, and the carry flag from A
Op Code [reg16] : 10011110 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101

Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 19

SBC HL,reg16
Operation Subtracts reg16 and the carry flag from HL.
Op Code 11101101 : 01[reg16]0010
Register Bit Field
BC 00
DE 01
HL 10
SP 11
Flags S Z C are affected as defined
H is set if a borrow from bit 12
P/V detects overflow
N is set
T States 15

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SUB

SUB A,reg8
Operation Subtracts reg8 from A.
Op Code 10010[reg8]
Register Bit Field
A 111
B 000
C 001
D 010
E 011
H 100
L 101
(HL) 110
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 4 or 7 (HL)

SUB A,imm8
Operation Subtracts the immediate value from A.
Op Code 11010110 : [imm8]
Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 7

SUB A,(regindex + ofs8)
Operation Subtracts the value at the memory location pointed to by regindex plus ofs8 from A
Op Code [reg16] : 10010110 : [ofs8]
Register Bit Field
IX 11011101
IY 11111101

Flags S Z H C are affected as defined
P/V detects overflow
N is set
T States 19

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This is part of Learn TI-83 Plus Assembly In 28 Days
Copyright (c) 2002, 2003, 2004 Sean McLaughlin
See the file gfdl.html for copying conditions